The invention relates to the field of generating a clock signal for digital systems, and in particular to a system for generating a line-coupled or color-carrier-coupled system clock signal for decoding a video signal.
In most integrated circuits (ICs) for video processing, especially in the area of digital television, a line-coupled or color-carrier-coupled clock signal is required which is coupled to the analog video signal (e.g., FBAS signal), and thus synchronized with this signal. In principle, two different couplings are possible—line coupling or color carrier coupling. In the first case, the horizontal sync pulses of the video signal are used as the reference for clocking, while in the second case, the color burst of the video signal is used.
Two different approaches are used to achieve the above-referenced coupling. In the first approach, the system clock provided for the respective IC is re-adjusted based on the synchronization signals contained in the FBAS signal. The analog-to-digital converter typically provided to digitize the FBAS signal is operated at the same system clock.
With the second system clock, the respective system, and thus the analog-to-digital converter, are free so that the FBAS signal is sampled asynchronously by the analog-to-digital converter. A digital circuit calculates the deviation between the actual sampling frequency and the virtual sampling frequency coupled to the FBAS signal (so-called skew value), and then corrects the asynchronous sampling values of the digitized FBAS signal.
Due to large-scale integration (e.g., “system on a chip”), it is necessary to accommodate both of the above methods on one IC since each method has advantages for specific system components. However, to use both methods simultaneously, the analog FBAS signal would have to be analog-to-digital-converted twice. The first analog-to-digital conversion is implemented using a free-running clock, that is, with an asynchronous clock signal not coupled to the FBAS signal. The second analog-to-digital conversion is implemented with a coupled and regulated clock signal. Due to its overall complexity, however, this approach is not feasible.
Increasingly, there are applications in which signals digitized at another location, such as FBAS signals or other signals, are already coupled with a clock. Such applications are found, for example, in personal computers in which the system clock is generally fixed and which determine the digitization and data sequence by predetermined processing groups.
There is a need for a system and method for generating a clock signal that is coupled to a reference signal.